Congratulations on getting your computer up and running. It's just a bit silly that the computer can only actually do what you burn into its EEPROM, and you can't communicate with it in any way. We'll fix that now. We'll add the first input – output circuit, namely the serial interface.
We will use the 6850, more precisely the 68B50 version (version B can also operate at 2 MHz). This is a circuit called ACIA – Asynchronous Communications Interface Adapter. Under the words „asynchronous communication interface“it is a bit strangely hidden that it is a standard serial interface, as we know from „COM ports“ and other serial ports on the computer. We connect some sort of USB-to-Serial converter to its outputs, giving us the ability to communicate with Alpha via a terminal program from the computer.
In our tests it turned out that even the MC6850 version, i.e. without „B“, can handle operation at this speed, but it may vary from piece to piece…
The 6850 circuit is a serial communication circuit. Its main task is to convert the sent byte into a serial signal (i.e., correctly transmit the start bit, data bits, possibly the parity bit, and finally the stop bit) and vice versa, i.e., read the correctly timed serial signal and prepare it for transmission to the processor.
Asynchronous in the description means that no clock signal is transmitted with the data, nor is the activity precisely timed - when a byte arrives, it is sent, when the input serial data arrives, it is read. It is the start and stop bits that ensure synchronisation, i.e. that what is to be read is actually read. By their correct progression the circuit knows that the data is OK.
The sending of data on the TXDATA output (Tx = transmit) and the receiving on the RXDATA input (Rx = receive) is timed by the system clock. For our computer, the system frequency is equal to 1.8432 MHz. This frequency is divided internally in ACIA (the divisor is programmable to values of 1, 16 and 64). We will use a division of 16, which means that the communication rate will be 1843200 / 16 = 115200 bits per second (baud).
The 6850 circuit communicates with the processor using an eight-bit data bus (D0-D7), several CS inputs (CS = ChipSelect) that determine when the circuit is communicating (CS0 = 1, CS1 = 1, /CS2 = 0 - in all other cases the data bus is disconnected), E input (Enable, the circuit only communicates when E=1), R/W input, which indicates whether the circuit is being read (1) or written (0), and RS input, which indicates whether data is being read/written (1) or control values(0).
In addition to these signals, it also offers the /IRQ (Interrupt Request – interrupt request) signal. With the interrupt, the ACIA can let the processor know that, for example, some data has arrived over the serial port, or that data to be sent has been sent, etc. We do not use interrupts.
Thus, from a programmer's point of view, the 6850 circuit appears as two registers (selected by the RS input), one of which is data, the other "system". The table will illuminate the function:
|Control Register (CR)|
|1||1||Read||Receive Data Register (RDR)|
Note that the control register can only be written to, not read from, while the status register can only be read from, not written to. It is not needed. Same with data registers - when reading, we read what the circuit received (and don't care what we sent). When writing, it is clear that we want to send data, it would not make sense to write to the received data.
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